Descripción de la oferta
MID Level - DFT & Post Silicon Validation Engineer Place: Barcelona, Spain Permanent We are hiring! Are you passionate about Design for Testability (DFT) for complex SoCs and SoC chiplets in package? We need you! As a Senior DFT and Post-Silicon Engineer, you will collaborate in the DFT implementation process, ensuring seamless integration with test and post-silicon validation teams. You will work with cutting-edge technology, collaborating closely with external IP providers, EDA vendors, and internal teams to deliver high-quality, high-performance SoCs or SiPs for mass production. Key Responsibilities Define and implement DFT architectures to improve testability, debug capabilities, and manufacturability. Ensure proper insertion of DFT features such as scan chains, BIST (Built-In Self-Test), and JTAG interfaces. Optimize DFT methodologies to minimize test time, reduce cost, and improve quality/yield. Test Development & Implementation. Develop and implement test plans and test strategies at silicon, package, and system levels. Define and develop automated test solutions for production and characterization. Ensure test coverage for all product development stages, from pre-silicon to mass production. Guarantee high yield on the final solution while considering chiplet complexities. Cross-Functional Collaboration. Work closely with design, validation, packaging, and operations teams to ensure seamless integration of testing and manufacturability. Collaborate with product management to ensure alignment with customer requirements and timelines. Process Improvement & Innovation. Continuously explore and implement new DFT methodologies and manufacturing processes. Lead initiatives for cost reduction, efficiency improvements, and quality enhancements in test and production. Reporting Structure Reports to: DFT and Post-Silicon Lead Requirements Bachelor’s, Master’s, or PhD in Computer Science, Electrical Engineering, or a related field. 4+ years of related experience. Proven experience with multiple tape-outs of high-performance SoCs or SiPs for mass production. Strong background in post-silicon test optimization and yield analysis. Experience in defining and implementing test strategies for high-volume production. Proficiency in RTL and testbench development using SystemVerilog and Verilog. Strong scripting skills (Shell, Tcl, Python3). Hands‑on experience with Tessent and SSN methods integrated with leading EDA design flows for advanced technology nodes is a plus. If you would like to learn more, please email directly #J-18808-Ljbffr
