Descripción de la oferta
Working for a cutting edge semiconductor company, based in Barcelona I have an exciting opportunity as HW Engineering Manager.You will be tasked with managing a team who are developing a RISC-V SOC.Applicants can come from an architecture, digital design or verification background.MUST HAVE - Deep understanding of ASIC, FPGA and SOC development processes.Must have experience:Degree / Masters / PhD in electronics / micro-electronics, physics or similar field
10+ years' experience of full chip design and delivery
Tech lead / team leadership / team management - circa 10+ people
ASIC / FPGA digital design - verilog, system verilog, VHDL
Significant experience of delivering: digital chips and complex processor based SOCs
CPU / GPU / RISC-V / MIPS / ISA / x86 processor knowledgeSOC design, architecture, integration
SOC interconnects - NOC IP, AXI, AMBA protocols etc
Strong understanding of high-speed digital products; SerDes, PCIe, ethernet, DDR, DRAM, HBM memories
Functional verification UVM
Formal verification - jasper gold, OneSpin, VC Formal, Mathworks, GitHub
Confident knowledge of the whole ASIC / SOC / chip design flow
Ability to demostrate multipe tape-out deliveries (silicon right first time etc)Bonus / preferred skills:
VPU (scalar, vector, matrix)
FPU - floating point algorithms / computer arithmetic
Compiler architecture
Compute architecure
System architecure
performance / modelling
